1. Field of the Invention
This invention relates to a semiconductor memory device and a method for manufacturing the semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having floating gate electrodes.
2. Background Art
Recently, with the increasing density of large scale integrated circuits (LSI), the gate insulating film and capacitor insulating film used in semiconductor memory devices have been constantly thinned. As a countermeasure to avoid the increase of leak current associated with the thinning, the structure of semiconductor memory devices is subjected to changes such as three-dimensional configuration. On the other hand, attempts have been made to prevent the increase of leak current by using high dielectric constant insulating film to increase physical film thickness.
In particular, in nonvolatile semiconductor memory devices such as electrically erasable programmable read-only memories (EEPROM), an interpoly dielectric film (IPD) or other interelectrode insulating film serving as a charge storage layer formed between the floating gate electrode and the control gate electrode is based on a laminated film such as silicon oxide (SiO2) film/silicon nitride (Si3N4) film/SiO2 film (ONO film) to increase dielectric constant. Furthermore, attempts are also made to apply a three-dimensional structure for increasing the area of the interelectrode insulating film. However, with the decrease of distance between memory cells in nonvolatile semiconductor memory devices, intercell interference is significantly increased due to lateral opposing capacitance between the floating gate electrodes of adjacent memory cells, causing write errors and degrading memory characteristics. Hence it is difficult to increase the area using three-dimensional structures.
For realizing next-generation nonvolatile semiconductor memory devices, the interelectrode insulating film needs to be based on an insulating film having higher dielectric constant than conventional ones. By using a high dielectric constant insulating film, it is possible to increase the capacitance of the interelectrode insulating film without increasing the area of the interelectrode insulating film. Hence there is no need to use three-dimensional structures, and the manufacturing process can be simplified. Consequently, the performance of memory cells is enhanced, and the method for manufacturing semiconductor memory devices is simplified. Thus a manufacturing method with high yield can be realized.
However, because of the increased intercell interference associated with the downscaling of nonvolatile semiconductor memory devices, the degradation of memory characteristics cannot be prevented simply by using a high dielectric constant insulating film as the interelectrode insulating film. For example, a low dielectric constant insulating film can be used as the device isolation insulating film isolating between floating gate electrodes of memory cell transistors adjacent in the row direction (word line direction) of the memory cell array to reduce lateral opposing capacitance between the floating gate electrodes opposed to each other.
In a technique for reducing lateral opposing capacitance between floating gate electrodes adjacent in the column direction (bit line direction), the distance between floating gate electrodes is increased by oxidizing the side face of the floating gate electrodes of adjacent memory cells. Furthermore, in a proposed technique for preventing the decrease of interelectrode insulating film capacitance due to the sidewall oxidation of floating gate electrodes and increasing the coupling ratio, a laminated film made of a high dielectric constant insulating film sandwiched by oxidizer barrier films is used as the interelectrode insulating film (see, e.g., JP 2005-197363A). When the floating gate electrode sidewall is oxidized, penetration of oxidizer through the high dielectric constant oxide film can be prevented by the oxidizer barrier film such as silicon nitride (Si3N4) film. Hence oxidation of the floating gate electrode and the control gate electrode in the vicinity of the interface with the interelectrode insulating film is prevented. The “coupling ratio” used herein refers to the ratio of interelectrode insulating film capacitance to the sum of tunnel insulating film capacitance and interelectrode insulating film capacitance.
However, because the oxidizer barrier films sandwiching the high dielectric constant insulating film decreases the interelectrode insulating film capacitance, the coupling ratio cannot be sufficiently increased in substance. Thus, unfortunately, it is difficult to achieve reduction in feature size and increase in packing density for nonvolatile semiconductor memory devices without decreasing the interelectrode insulating film capacitance while preventing intercell interference.